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Hitachi America, Ltd.

Hitachi

Hitachi America, Ltd., Research & Development

System LSI

SRL plays a critical role in the design and architecture of Hitachi's SuperH family of RISC microprocessors used in portable communications, applications and computing. One of SRL's most significant contributions was the development of the first hybrid RISC/DSP microprocessor in 1995. This processor combines the 16-bit RISC instructions and rich peripherals of an SH2/3 micro controller with the fixed-point number-crunching capability of a Texas Instruments C54x DSP. A single SH-DSP chip can often replace dual controller/DSP solutions, thus reducing total system cost as inter-processor communication is eliminated.

  • kelysville.wmv
    This Windows Media clip represents the quality that can be expected using Hitachi's SH3-DSP processor at 133MHz.

SuperH - Digital Signal Processor (SH-DSP)

Hitachi's SH3-DSP processor, at 133MHz with 16KB cache, is ideal for network and communications applications, including VoIP and streaming audio/video compression/decompression (CODEC) in PDA and cell phone form factors. Since 1998, SRL has contributed to the enhancement of the SH processor and designed the multimedia instruction-set, branch/fetch architectures and implemented mixed-mode PLL circuits for the SH5 processor, a joint venture between ST Microelectronics and Hitachi, Ltd.

In addition to designing the instruction-set architecture for SuperH processors, SRL has developed a large portfolio of multimedia software which is distributed via Hitachi Semiconductor (America), Inc., SuperH, Inc. and Hitachi, Ltd.

SuperH - Digital Signal Processor (SH-DSP)

Streaming Media

As broadband Internet connections to homes, and portable wireless devices proliferate, the transfer of music, speech, and video images over the Internet becomes possible. SRL has made strong relationships with industry leaders in this field to make their proprietary software work efficiently on Hitachi's DSP-capable processors. Both Microsoft Windows Media Technology and Real Networks technology is now supported. MPEG4 standards are also available.

Voice-over Internet Protocol (VoIP)

Targeting video conferencing as an emerging application for Internet Protocol consumers, SRL developed SH-DSP software for speech compression, (VoIP) video CODEC, and line/acoustic echo cancellation software. This lead to Voice over Internet Protocol (VoIP) initiatives with Cisco Systems and other partners. SRL demonstration systems support signalling protocol technologies including ITU H.323, session initiation protocol (SIP), and media gateway control protocol (MGCP).

SH-Mobile

Hitachi this year announced its Application Processor for mobile phones and PDA. SRL is playing an important role in developing software and accelerators for this SH-3-DSP based platform and supporting its promotion in North America. In addition to integrations standards-based software, we are optimizing and integrating technology from such partners as Microsoft, RealNetworks, Verance, Sony, PointBase, EyeMatic, and OpenWave. A longer term goal is to accelerate software with a flexible SoC engine which provides speed-up of pure LSI circuits combined with the programmability of a micro-computer.

In the area of System-chip technology, SRL has defined a SoC integration platform targeting the US Broadband Access and Car Information System (CIS) markets. These platforms utilize SH capabilities in a real-world environment and provide software development platforms that define SH-based application-specific system LSIs. Our work encompasses development and use of instruction set simulators and virtual models of processors, development of application software both in processor-optimized assembly as well as in encapsulated system modeling languages, modeling system architecture components, and integrating the entire system using state-of-the-art co-design

and co-verification tools from leading EDA vendors such as Cadence and Co-Ware.

SRL has established a tradition in collaborating with leading institutions in North America and Europe to foster state-of-the-art research and development. We have collaborated with universities such as Penn State University in developing low power microprocessor architectures, University of California at Berkeley, Ptolemy Group in the area of visual programming and systems modeling, and the University of California at Davis for digital circuit design. We have recently completed a project with the

University of Edinburgh in Scotland on developing networking software for wireless LANs. We are currently collaborating with the Berkeley Wireless Research Center for sensor networks and ultra-wideband wireless technology.

Professional Activities

  • Member of Technical Program Committee of the 1997 IEEE International Conference on High Performance Computing
  • Chair and organizer of the session on Low Power at the 1998 IEEE Computer Elements Workshop
  • Represents Hitachi on Wi-Fi
  • Active in IEEE 802.11 standardization

Referred Publications

  • "Instruction Buffering to Reduce Power in Processors for Signal Processing,"
    R. S. Bajwa, M. Hiraki, H. Kojima, D. Gorney, K. Nitta, A. Shridhar, K. Seki, and K. Sasaki,
    IEEE Transactions on VLSI Systems, pp. 417-424, December 1997.
  • "Asynchronous Processor Survey,"
    T. Werner and V. Akella,
    IEEE Computer, Vol. 30, No. 11, pp. 67-76, November 1997.
  • "Power Analysis of a 32-bit RISC Microcontroller Integrated with a 16-bit DSP"
    R. S. Bajwa, N. Schumann and H. Kojima,
    in the proceedings of the 1997 International Symposium on Low Power Electronics and Design, pp. 137-142, August 1997.
  • "Optimized Software Synthesis for Synchronous Dataflow,"
    S. S. Bhattacharyya, P. K. Murthy, and E. A. Lee,
    International Conference on Application Specific Systems, Architectures, and Processors, July, 1997, invited paper.
  • "Optimizing Synchronization in Multiprocessor DSP Systems,"
    S. S. Bhattacharyya, S. Sriram, and E. A. Lee,
    IEEE Transactions on Signal Processing, June, 1997.
  • “PGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations,”
    S. S. Bhattacharyya, P. K. Murthy, and E. A. Lee,
    Journal of Design Automation for Embedded Systems, January, 1997.
  • "Latency-constrained Resynchronization for Multiprocessor DSP Implementation,”
    S. S. Bhattacharyya, S. Sriram, and E. A. Lee,
    International Conference on Application Specific Systems, Architectures, and Processors, August, 1996.
  • "Self-timed Resynchronization: A Post-optimization for Static Multiprocessor Schedules,"
    S. S. Bhattacharyya, S. Sriram, and E. A. Lee,
    International Parallel Processing Symposium, April, 1996.
  • "Integrating a DSP with a Microcontroller,"
    A. Shridhar and K. Nitta,
    The Signal Processing Applications Conference at DSPx96, March 1996.
  • "Software Synthesis from Dataflow Graphs,"
    S. S. Bhattacharyya, P. K. Murthy, and E. A. Lee,
    Kluwer Academic Publishers, 1996.
  • "Optimal Parenthesization of Lexical Orderings for Block Diagram DSP Programs, "
    S. S. Bhattacharyya, P. K. Murthy, and E. A. Lee,
    International Workshop on VLSI Signal Processing, October, 1995.
  • "Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor Systems,"
    S. S. Bhattacharyya, S. Sriram, and E. A. Lee,
    International Conference on Application Specific Array Processors, July, 1995.
  • "Converting Graphical DSP Programs into Memory-constrained Software Prototypes,"
    S. S. Bhattacharyya, P. K. Murthy, and E. A. Lee,
    International Workshop on Rapid Systems Prototyping, June, 1995.